AUC AUP AVC Family


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___Part No.___
______
(勾選方式)
___Description___
___Technology family___
______
(勾選方式)
___Number of channels___
______
(勾選方式)
___Sub family___
______
(勾選方式)
___Function___
______
(勾選方式)
VCC(V)
Min

(Range)
VCC(V)
Max

(Range)
tPD(nS)
Max

(Range)
ICC(uA)
Max

(Range)
Output Driver Iout(mA)
Max

(Range)
___Package___
______
(勾選方式)
___U74AUC1G00___
___SINGLE 2-INPUT NAND GATE___
___AUC___
___1___
___NAND GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.3
10
9
___SOT-23-5___
___SOT-353___
___U74AUC1G02___
___SINGLE 2-INPUT NOR GATE___
___AUC___
___1___
___NOR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.2
10
9
___SOT-23-5___
___SOT-353___
___U74AUC1G08___
___SINGLE 2-INPUT AND GATE___
___AUC___
___1___
___AND GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.4
10
9
___SOT-23-5___
___SOT-353___
___U74AUC1G32___
___SINGLE 2-INPUT POSITIVE-OR___
___GATE___
___AUC___
___1___
___OR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.4
10
9
___SOT-23-5___
___SOT-353___
___U74AUC1G86___
___SINGLE 2-INPUT___
___EXCLUSIVE-OR GATE___
___AUC___
___1___
___XOR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.5
10
9
___SOT-23-5___
___SOT-353___
___U74AUC1G125___
___SINGLE BUS BUFFER GATE___
___WITH 3-STATE OUTPUT___
___AUC___
___1___
___BUFFER___
___3-state output___
___OE pin___
___Ioff supports partial-power-down mode operation___
0.9
2.7
3.5
10
9
___SOT-25___
___SOT-353___
___U74AUC1G126___
___SINGLE BUS BUFFER GATE___
___WITH 3-STATE OUTPUT___
___AUC___
___1___
___BUFFER___
___3-state output___
___OE pin___
___Ioff supports partial-power-down mode operation___
0.9
2.7
3.5
10
9
___SOT-25___
___SOT-353___
___U74AUC2G04___
___DUAL INVERTER GATE___
___AUC___
___2___
___INVERTER___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
4.5
10
9
___SOT-26___
___SOT-363___
___U74AUC2G34___
___DUAL BUFFER GATE___
___AUC___
___2___
___BUFFER___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
2.7
5.8
10
9
___SOT-26___
___SOT-363___
___U74AVC1T45___
___SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS___
___AVC___
___1___
___TRANSCEIVER___
___push-pull output___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
1.2
3.6
3.8
10
12
___SOT-363___
___SOT-26___
___U74AUC125___
___QUADRUPLE BUS BUFFER___
___GATE WITH 3-STATE OUTPUTS___
___AUC___
___4___
___BUFFER___
___3-state output___
___OE pin___
___Ioff supports partial-power-down mode operation___
0.8
2.7
2.1
10
9
___TSSOP-14___
___U74AUC244___
___OCTAL BUFFER/DRIVER WITH___
___3-STATE OUTPUTS___
___AUC___
___8___
___BUFFER___
___3-state output___
___OE pin___
___Ioff supports partial-power-down mode operation___
0.8
2.7
1.9
20
9
___SSOP-20___
___U74AUP1G00___
___SINGLE 2-INPUT NAND GATE___
___AUP___
___1___
___NAND GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.5
0.5
4
___SOT-23-5___
___SOT-353___
___DFN1010-6___
___U74AUP1G02___
___SINGLE 2-INPUT NOR GATE___
___AUP___
___1___
___NOR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.7
0.5
4
___SOT-23-5___
___SOT-353___
___X2DFN1010-6___
___U74AUP1G04___
___SINGLE INVERTER GATE___
___AUP___
___1___
___INVERTER___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
5.4
0.5
4
___SOT-23-5___
___SOT-353___
___SOT-25___
___X2DFN1010-6___
___X2DFN0808-4___
___U74AUP1G06___
___LOW-POWER SINGLE INVERTER BUFFER/DRIVER___
___WITH OPEN-DRAIN OUTPUTS___
___AUP___
___1___
___INVERTER___
___open-drain output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
10.5
0.5
4
___SOT-23-5___
___SOT-353___
___X2DFN1010-6___
___U74AUP1G07___
___BUFFER WITH OPEN-DRAIN OUTPUT___
___AUP___
___1___
___BUFFER___
___open-drain output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
6.3
0.5
4
___SOT-23-5___
___SOT-353___
___X2DFN1010-6___
___X2DFN0808-4___
___U74AUP1G08___
___2-INPUT AND GATE___
___AUP___
___1___
___AND GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.7
0.5
4
___SOT-23-5___
___SOT-353___
___SOT-553___
___X2DFN1010-6___
___X2DFN0808-4___
___U74AUP1G14___
___LOW-POWER SINGLE___
___SCHMITT-TRIGGER INVERTER___
___AUP___
___1___
___INVERTER___
___push-pull output___
___schmitt-trigger___
___Ioff supports partial-power-down mode operation___
0.8
3.6
6.2
0.5
4
___SOT-25___
___SOT-23-5___
___SOT-353___
___U74AUP1G32___
___SINGLE 2-INPUT OR GATE___
___AUP___
___1___
___OR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
7
0.5
4
___SOT-23-5___
___SOT-353___
___DFN1010-6___
___DFN1410-6___
___U74AUP1G38___
___LOW-POWER 2-INPUT NAND___
___GATE WITH OPEN-DRAIN___
___OUTPUT___
___AUP___
___1___
___NAND GATE___
___open-drain output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
12.7
0.5
-
___SOT-23-5___
___SOT-353___
___U74AUP1G57___
___LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE___
___AUP___
___1___
___MULTIPLEXER___
___multiplexer___
___schmitt-trigger___
___Ioff supports partial-power-down mode operation___
0.8
3.6
5.8
0.5
4
___SOT-363___
___X1DFN14510-6___
___U74AUP1G74___
___LOW-POWER SINGLE___
___POSITIVE EDGE TRIGGERED___
___D-TYPE FLIP-FLOP WITH___
___CLEAR AND PRESET___
___AUP___
___1___
___D-TYPE FLIP-FLOP___
___push-pull output___
___CLR pin___
___Ioff supports partial-power-down mode operation___
0.8
3.6
7
0.5
4
___DFN2030-8___
___CDFN2030-8___
___TSSOP-8___
___U74AUP1G86___
___SINGLE 2-INPUT___
___EXCLUSIVE-OR GATE___
___AUP___
___1___
___XOR GATE___
___push-pull output___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.4
0.5
4
___SOT-23-5___
___SOT-353___
___DFN1010-6___
___U74AUP1G97___
___LOW-POWER CONFIGURABLE___
___MULTIPLE-FUNCTION GATE___
___AUP___
___1___
___MULTIPLEXER___
___multiplexer___
___schmitt-trigger___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.7
0.5
4
___SOT-26___
___SOT-363___
___X2DFN1010-6___
___U74AUP1G126___
___SINGLE BUS BUFFER GATE___
___WITH 3-STATE OUTPUT___
___AUP___
___1___
___BUFFER___
___3-state output___
___OE pin___
___Ioff supports partial-power-down mode operation___
0.8
3.6
4.8
0.5
4
___SOT-23-5___
___SOT-353___
___DFN1010-6___
___U74AUP1T34___
___1-BIT UNIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR___
___AUP___
___1___
___TRANSCEIVER___
___push-pull output___
___Ioff supports partial-power-down mode operation___
___volage-level translator___
0.9
3.6
4.28
5
6
___SOT-23-5___
___SOT-353___
___U74AUP1T57___
___SINGLE-SUPPLY___
___VOLTAGE-LEVEL___
___TRANSLATOR WITH NINE___
___CONFIGURABLE GATE LOGIC___
___FUNCTIONS___
___AUP___
___1___
___MULTIPLEXER___
___multiplexer___
___schmitt-trigger___
___Ioff supports partial-power-down mode operation___
___volage-level translator___
2.6
3.6
4.8
0.5
4
___SOT-363___
___U74AUP1T157___
___SINGLE 2-INPUT___
___SCHMITT-TRIGGER BUFFER___
___MULTIPLEXER___
___(NONINVERTED)___
___AUP___
___1___
___MULTIPLEXER___
___multiplexer___
___schmitt-trigger___
___Ioff supports partial-power-down mode operation___
___volage-level translator___
2.3
3.6
4.4
0.5
4
___SOT-363___
___U74AVC2T45___
___DUAL-BIT DUAL SUPPLY, BUS TRANSCEIVER WITH CONFIGURABLE___
___LEVEL-SHIFTING AND TRANSLATION___
___AVC___
___2___
___TRANSCEIVER___
___push-pull output___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
1.2
3.6
2.4
10
12
___SOP-8___
___U74AVC2T245___
___2-BIT DUAL-SUPPLY BUS___
___TRANSCEIVER___
___WITH CONFIGURABLE___
___VOLTAGE TRANSLATION AND___
___3-STATE OUTPUTS___
___AVC___
___2___
___TRANSCEIVER___
___3-state output___
___OE pin___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
1.2
3.6
2.7
16
12
___SOP-14___
___QFN10-(1.8x1.4)___
___U74AVC4T245___
___4 BIT DUAL-SUPPLY BUS TRANSCEIVER___
___WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS___
___AVC___
___4___
___TRANSCEIVER___
___3-state output___
___OE pin___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
1.2
3.6
2.8
8
12
___SOP-16___
___TSSOP-16___
___QFN-16(3.5×2.5)___
___X1QFN-16(1.8×2.6)___
___U74AVC4TD245___
___4-BIT DUAL SUPPLY___
___TRANSLATING___
___TRANSCEIVER WITH___
___CONFIGURABLE VOLTAGE___
___TRANSLATION; 3-STATE___
___AVC___
___4___
___TRANSCEIVER___
___3-state output___
___OE pin___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
0.8
3.6
6
8
12
___TSSOP-16___
___U74AVCH2T45___
___2-BIT, 2-SUPPLY, BUS___
___TRANSCEIVER WITH___
___CONFIGURABLE___
___LEVEL-SHIFTING AND___
___TRANSLATION AND 3-STATE___
___OUTPUTS___
___AVC___
___2___
___TRANSCEIVER___
___3-state output___
___Direction (DIR) pin___
___Ioff supports partial-power-down mode operation___
1.2
3.6
2.1
10
12
___SOP-8___